Method for accessing memory

ABSTRACT

The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/594,922, filed on May 19, 2005 and entitled “REPROGRAMMABLE OTP”, thecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for accessing a memory,especially to a method for accessing a one time programmable (OTP)memory.

2. Description of the Prior Art

Recently, non-volatile memories are widely adopted in all kinds ofelectronic products such as cell phones, digital cameras, and digitalmusic players. These non-volatile memories are usually hard drives,flash memories, and OTP memories. Flash memories and OTP memories aretwo common types of memories. The major difference between these twokinds of memories is that a flash memory is refreshable while an OTPmemory can only be written once. More specifically, a flash memory iscapable of being read and written many times, but once an OTP memory isprogrammed, i.e., when some data are written into an OTP memory, the OTPmemory can no longer be utilized to store another data.

A flash memory is a multi-time programmable (MTP) memory which iscapable of being repeatedly written and erased, and therefore a flashmemory requires some circuits that perform the erase, write, and readoperations. However, an OTP memory requires only write and readoperations but no erase operation; therefore, compared to an MTP memory,an OTP memory does not require a circuit to perform the erase operation.The simplicity of an OTP memory leads to a simpler and low-costmanufacturing process of the circuit of the OTP memory. Under acircumstance where only a few read and write processes are required, aplurality of OTP memories is often utilized to simulate an MTP memory.As a result, the performance of a MTP memory can be achieved without anadditional erase circuit.

U.S. Pat. No. 6,728,137 discloses a method for performing the read andwrite operations on an OTP memory. A plurality of OTP memories isutilized to simulate an MTP memory. Please refer to FIG. 1. FIG. 1 showsa circuit configuration of a memory device. The memory device 100contains an OTP memory area 110, a control circuit 120, a row decoder130, a column decoder 140, and a record element 150. The OTP memory area110 contains N OTP memory blocks 112, and every OTP memory block 112contains a plurality of memory cells (not shown). Each memory cellstores a data of one bit. Since every memory cell is one timeprogrammable, programmed memory cells cannot be written into new data,i.e., cannot be programmed again. The record element 150 consists of aplurality of record units 152, each of which contains one or more thanone memory cell(s). Every record unit 152, which correspondsrespectively to an OTP memory block 112, stores the usage status of itscorresponding OTP memory block 112. For example, the record unit Astores the usage status of the OTP memory block #1, the record unit Bstores the usage status of the OTP memory block #2, and so on. Accordingto the embodiment disclosed in this patent, if some record unit 152stores a data of “0”, the OTP memory block 112 corresponding to thisrecord unit 152 is an un-programmed OTP memory block; however, if somerecord unit 152 stores a data of “1”, the OTP memory block 112corresponding to this record unit 152 is a programmed OTP memory block.Please note that the minimum units of the OTP memory area 110 and therecord element 150 are memory cells such that the same manufacturingmethod can be applied on both the OTP memory area 110 and the recordelement 150.

The control circuit 120, which is coupled to the record element 150, therow decoder 130, and the column decoder 140, outputs a control signalaccording to the data stored in the record element 150. After beingdecoded by the row decoder 130 and the column decoder 140, the controlsignal selects a proper OTP memory block 112 for being programmed orbeing read. Although the OTP memory blocks 112 contained in the OTPmemory area 110 can only be programmed once and the stored data cannotbe replaced by a new data, an MTP memory is able to be simulated byutilizing a plurality of OTP memory blocks 112 along with a propercontrol method.

The patent mentioned above discloses a method that utilizes a recordelement 150 outside the OTP memory area 110 to record the usage statusof every OTP memory block 112. The control circuit 120 selects a properOTP memory block 112 to program or read by reading the data stored inthe record element 150.

SUMMARY OF THE INVENTION

Therefore, it is an object of the claimed invention to provide a methodfor accessing a memory. In this method, no additional record units arerequired to record the usage status of any memory block.

According to an embodiment of the claimed invention, a method foraccessing a memory device is disclosed. The memory device comprises atleast one OTP memory block, and each memory block comprises a firstmemory section and a second memory section. The method comprises:selecting a first target memory block; reading the first target memoryblock; and if the first memory section of the first target memory blockstores a first data, a predetermined value is outputted as the valuestored in the first target memory block, and if the first memory sectionof the first target memory block stores a second data, the value storedin the second memory section of the first target memory block isoutputted as the value stored in the first target memory block.

According to an embodiment of the claimed invention, a method foraccessing a memory device is disclosed. The memory device comprises atleast one OTP memory block. Each memory block comprises a first memorysection and a second memory section, and before an OTP memory block isprogrammed, each memory cell of the OTP memory block stores a firstlogic value. The method comprising: selecting a first target memoryblock; and programming the second memory section of the first targetmemory block such that the second memory section stores a predeterminedvalue to erase the first target memory block.

According to an embodiment of the claimed invention, a method foraccessing a memory device is disclosed. The memory device comprises atleast one OTP memory block. Each memory block comprises a first memorysection and a second memory section, and before an OTP memory block isprogrammed, each memory cell of the OTP memory block stores a firstlogic value. The method comprising: selecting a target memory block; andwriting a to-be-written data to the target memory block, wherein if theto-be-written data corresponds to a predetermined value, program onlythe first memory section of the target memory block to store a firstdata, and if the to-be-written data does not correspond to thepredetermined value, program the second memory section of the targetmemory block according to the to-be-written data.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit configuration of a prior art memory device.

FIG. 2 shows a circuit configuration of a memory device according to thepresent invention.

FIG. 3 shows the inner circuit configuration of the OTP memory blockshown in FIG. 2.

FIG. 4 shows a first status of the memory device shown in FIG. 2.

FIG. 5 shows a second status of the memory device shown in FIG. 2.

FIG. 6 shows a third status of the memory device shown in FIG. 2.

FIG. 7 shows a fourth status of the memory device shown in FIG. 2.

FIG. 8 shows a fifth status of the memory device shown in FIG. 2.

FIG. 9 is a diagram illustrating the sequential search.

FIG. 10 is a diagram illustrating the binary search.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 shows a preferred embodiment of thepresent invention. The memory device 200 shown in FIG. 2 contains an OTPmemory area 210, a control circuit 220, a row decoder 230, and a columndecoder 240. The OTP memory area 210 contains a plurality of OTP memoryblocks 212. Please refer to FIG. 3. FIG. 3 shows the inner circuitconfiguration of the OTP memory block 212. Each OTP memory block 212consists of a plurality of memory cells 214. Like the memory cells ofthe prior art memory device 100, each memory cell 214 stores a data of 1bit. In this embodiment, the plurality of memory cells 214 can bedivided into two sections, i.e., every OTP memory block contains a firstmemory section 320 and a second memory section 310. Each memory sectioncontains one or more than one memory cell(s). In this embodiment, thefirst memory section 320 contains the last memory cell 214 of the OTPmemory block 212, and the second memory section 310 contains all othermemory cells 214 except it does not contain the last memory cell 214.

Please refer to FIG. 2. The control circuit 220 determines how to selecta proper OTP memory block 212, and controls how to write or read everymemory cell 214 in the OPT memory block 212. The control signaloutputted by the control circuit 220 is first decoded by the row decoder230 and the column decoder 240, and then a specific OTP memory block 212can be selected by the control circuit 220 according to the decodedcontrol signal. Consequently, the control circuit 220 writes or readsthe memory cells 214 of the selected OTP memory block 212.

The following is a description of a method of accessing a specificmemory block 212. Please note that every memory cell 214 of the OTPmemory block 212 has a logic value status (e.g., logic value “1”) whenthe memory cell 214 is un-programmed, and has a different logic valuestatus (e.g., logic value “0”) when the memory cell 214 is programmed.Please refer to FIG. 4. FIG. 4 is an inner circuit of the OTP memoryarea 210 shown in FIG. 2. In the following embodiment, eight OTP memoryblocks 212, which are re-named 401˜408, are taken as an example toillustrate the steps of accessing the memory blocks 401˜408. However,the number of OTP memory blocks shown in this example is not meant to bea limitation of the present invention. In this example, it is given thatmemory blocks 401˜408 each contain 9 memory cells 214, and these 9memory cells 214 are divided into two sections, i.e., the first memorysection 320 and the second memory section 310. The second memory section310 contains 8 memory cells capable of storing a data of 8 bits, and thefirst memory section 320 contains the remaining memory cell capable ofstoring a data of 1 bit. Before the OTP memory area 210 is programmed,all memory cells 214 of the OTP memory blocks 401˜408 have the samelogic value of “1”. The sequence of utilizing the OTP memory blocks401˜408 proceeds from top to bottom, i.e., the first OTP memory block tobe utilized is the memory block 401, the second memory block to beutilized is the memory block 402, and so on. The memory block 401 isselected for the first writing process. Assuming that the value to bewritten is 70, hence the data “01000110” corresponding to the value 70is written into the OTP memory block 401. The updated status of the OTPmemory area 210 is shown in FIG. 5. When reading, the control circuit220 initially reads every second memory section 310 of every OTP memoryblock 212 in the OTP memory area 210, and determines the first OTPmemory block whose second memory section 310 does not store the logicvalue representing an erased OTP memory block. In this case, it is OTPmemory block 401 that is the first OTP memory block whose second memorysection 310 does not store the logic value representing an erased OTPmemory block. Therefore, when next reading the OTP memory area 210, thecontrol circuit 220 selects the OTP memory block 401. The data stored inthe first memory section 320 is first checked. Because the present datastored in the first memory section 320 is “1”, the data stored in thesecond memory section 310 is then read. As a result, a value of 70 isoutputted according to the read data “01000110”. When it is required tofurther write data in the OTP memory area 210, an operation of “erase”is required to be performed on the presently utilized OTP memory block401. For an OTP memory block, there is not actually an erase operation.In the present invention, an OTP memory block is identified as beingerased by storing a predetermined data in the second memory section 310.For example, assuming that the predetermined data is a data whosehighest two bits are “0” (e.g., “00xxxxxx”), such as “00111111”, whichcorresponds to a value of 63, then whenever the status of the secondmemory section 310 is “00111111”, the corresponding OTP memory block isidentified as being an erased memory block. However, when the value tobe stored in an OTP memory block happens to correspond to the data whosehighest two bits are “0” (e.g., “00xxxxxx”), such as “00111111”, thenthe status of the second memory section 310 is left as “11111111”, andthe data stored in the first memory section 320 is changed from “1” to“0” for identifying that the present value stored in the OTP memoryblock is 63, which corresponds to the predetermined data “00111111”.When selecting an OTP memory block to be accessed, the control circuit220 manages to determine the first OTP memory block having a secondmemory section 310 whose two highest bits are not “0”. In thisembodiment, the predetermined data is set to be all 0 (i.e.,“00000000”), which means when the data stored in the first memorysection 320 is “0”, the value stored in the corresponding OTP memoryblock is zero. In short, in this embodiment, the OTP memory block 401 isidentified as being erased by changing the logic values of all thememory cells of the second memory section 310 to 0. The erased status isshown in FIG. 6. All the memory cells of the second memory section 310of the OTP memory block 401 store the same logic value 0. After theerase operation is completed, it's allowable to write a second value tothe next OTP memory block.

Before the process of writing a second value to an OTP memory block, thelogic values of all the memory cells of the second memory section 310 ofthe OTP memory block must be 1. An OTP memory block having all memorycells of logic value 1 is an un-programmed OTP memory block. There maybe several un-programmed OTP memory blocks at the same time, but onlythe first un-programmed OTP memory block will be selected for havingdata written to it since the sequence of utilizing the OTP memory blocksin the OTP memory area 210 proceeds from top to bottom. For this presentembodiment, the OTP memory block 402 is selected to be written into thesecond data. Here the section value is set to be zero, which correspondto a data of “00000000”. If the memory cells of the second memorysection 310 of the OTP memory block 402 are all programmed to be 0, theOTP memory block 402 will be considered as an erased OTP memory block.Therefore, when the data to be written is zero, the first memory section320 is programmed instead of the second memory section 310. The memorycell of the first memory section 320 is programmed to be a logic value0, which represents that the value stored in the OTP memory block 402 iszero. FIG. 7 shows the status after the second value is written.

Before the next reading process, an OTP memory block is selected bycomparing every second memory section 310 of each OTP memory block. Thestatus of the second memory section 310 of the selected OTP memory blockis not “00000000”. The OTP memory blocks above the selected OTP memoryblock are all erased, i.e., the second memory sections 310 thereof havethe same status of “00000000”, and the OTP memory blocks under theselected OTP memory block are all un-programmed, i.e., statuses of thefirst memory section 320 and the second memory section 310 arerespectively “1” and “11111111”. Therefore, in this embodiment, the OTPmemory block 402 is selected. In the reading process, the data stored inthe first memory section 320 is first read. Since the data stored in thefirst memory section 320 is 0, i.e., the value stored in the OTP memoryblock 402 is zero, a value of 0 is obtained in the reading process.

Next, in the erase process, an OTP memory block is selected by comparingevery second memory section 310 of each OTP memory block. The status ofthe second memory section 310 of the selected OTP memory block is not“00000000”. The OTP memory blocks above the selected OTP memory blockare all erased, i.e., the second memory sections 310 thereof have thesame status of “00000000”, and the OTP memory blocks under the selectedOTP memory block are all un-programmed, i.e., statuses of the firstmemory section 320 and the second memory section 310 are respectively“1” and “11111111”. Therefore, in this embodiment, the OTP memory block402 is selected. When the OTP memory block 402 is erased, the status ofthe second memory section 310 is programmed to be “00000000”, as shownin FIG. 8.

The above-mentioned writing, reading and erasing processes can berepeated until all the OTP memory blocks in the OTP memory area 210 areprogrammed.

In the present invention, two major searching rules are adopted toperform the selection of the proper OTP memory block. These twosearching rules serve as exemplary examples to illustrate the searchingprocedure, but are not meant to a limitation of the present invention.The first searching rule is a sequential search. Please refer to FIG. 9.Here, the exemplary example also utilizes 8 OTP memory blocks toillustrate the searching procedure. During the reading, erasing orwriting process, the control circuit 220 checks if the status of thesecond memory section 310 of the OTP memory block 401 is all 0 (i.e.,“00000000”). If it is true, then the control circuit 220 checks the nextOTP memory block, i.e., the OTP memory block 402. The control circuit220 checks all the OTP memory blocks in sequence until it finds thefirst OTP memory block having a second memory section 310 whose statusis not all 0 (i.e., “00000000”) The OTP memory block is the selected OTPmemory block. If the initial status of the second memory section 310 ofthe selected memory block is not all 1 (i.e., “11111111”), i.e., theselected memory block is programmed, then the to-be-written data of thepresent writing process along with the previously written data will forma joint data. For example, if the previously written data is “10111111”and the to-be-written data is “11110010”, then the status of the secondmemory section 310 of the selected OTP memory block will be “10110010”after the present writing process is completed. In short, even if theinitial statuses of the second memory section 310 and the first memorysection 320 are not all 1, the writing process can still be performed.However, the written data may not be read out correctly.

The second searching rule is a binary search. Please refer to FIG. 10.When performing the first search procedure, the control circuit 220initially checks the middle OTP memory block of all the OTP memoryblocks. Therefore, in this embodiment, the control circuit 220 firstchecks the OTP memory block 404. During the reading, erasing, or writingprocess, the control circuit 220 checks the status of the second memorysection 310 of the OTP memory block 404. A status of the second memorysection 310 of the OTP memory block 404 being all 0 (i.e., “00000000”)means that the OTP memory blocks 401˜404 are all erased. In this case,the control circuit 220 follows the direction of the solid line toperform the second check on the OTP memory block 406. However, if thestatus of the second memory section 310 of the OTP memory block 404 isnot all 0 (i.e., not “00000000”) and not all 1 (i.e., not “11111111”),then the control circuit 220 selects the OTP memory block 404. If thestatus of the second memory section 310 of the OTP memory block 404 isall 1 (i.e., “11111111”), the control circuit 220 further checks thestatus of the first memory section 320 of the OTP memory block 404. Astatus of the first memory section 320 of the OTP memory block 404 being0 means that the OTP memory block 404 already stores a value of 0. As aresult, the control circuit 220 determines the OTP memory block 404 asthe present selected OTP memory block. However, a status of 1means thatall the OTP memory blocks under the OTP memory block 404 areun-programmed. If the status of the first memory section 320 of the OTPmemory block 404 is “1”, the control circuit 220 follows the directionof the dotted line to perform the second check on the OTP memory block402. However, regardless of performing the second check on the OTPmemory block 402 or 406, the above-mentioned rule is repeated until thefirst OTP memory block having a second memory section 310 whose statusis not all 0 is found. This OTP memory block is the present selected OTPmemory block. Similarly, if the initial status of the second memorysection 310 of the selected OTP memory block is not all 1 (i.e., not“11111111”), i.e., the selected OTP memory block is programmed, then theto-be-written data of the present writing process along with thepreviously written data will form a joint data. For example, if thepreviously written data is “10111111” and the to-be-written data is“11110010”, then the status of the second memory section 310 of theselected OTP memory block will be “10110010” after the present writingprocess is completed. In short, even if the initial statuses of thesecond memory section 310 and the first memory section 320 are not all1, the writing process can still be performed. However, the written datamay not be read out correctly.

In summary, either sequential search or binary search primarily checksthe status of the second memory section 310 of the OTP memory block. Aproper OTP memory block is selected by comparing the statuses of thesecond memory sections 310 of the OTP memory blocks, and then thereading, erasing, or writing process is performed on the selected OTPmemory block. In short, in the present invention, by dividing an OTPmemory block into two memory sections (i.e., the first memory section320 and the second memory section 310), the memory device does notrequire additional record units to record the usage status (e.g.,un-programmed or programmed) of each OTP memory block. A proper OTPmemory block can be selected by merely performing a compare procedure.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method for accessing a memory device, the memory device comprisingat least one one-time-programmable (OTP) memory block, and each memoryblock comprising a first memory section and a second memory section, themethod comprising: selecting a first target memory block; reading thefirst target memory block; and if the first memory section of the firsttarget memory block stores a first data, a predetermined value isoutputted as the value stored in the first target memory block, and ifthe first memory section of the first target memory block stores asecond data, the value stored in the second memory section of the firsttarget memory block is outputted as the value stored in the first targetmemory block.
 2. The method of claim 1, wherein before an OTP memoryblock is programmed, each memory cell of the OTP memory block stores afirst logic value, and the method further comprises: programming thesecond memory section of the first target memory block such that thesecond memory section stores the predetermined value to erase the firsttarget memory block.
 3. The method of claim 2, wherein the memory devicecomprises a plurality of OTP memory blocks arranged in sequence, and themethod further comprises: writing a to-be-written data to a secondtarget memory block that is after the first target memory block, whereinif the to-be-written data corresponds to the predetermined value,program only the first memory section of the second target memory blockto store the first data, and if the to-be-written data does notcorrespond to the predetermined value, program the second memory sectionof the second target memory block according to the to-be-written data.4. The method of claim 1, wherein the memory device comprises M OTPmemory blocks, and the step of selecting the first target memory blockfurther comprises: comparing the second memory sections of N OTP memoryblocks from the M OTP memory blocks according to a search rule to selectthe first target memory block.
 5. The method of claim 4, wherein thesearch rule is a sequential search or a binary search.
 6. A method foraccessing a memory device, the memory device comprising at least oneone-time-programmable (OTP) memory block, each memory block comprising afirst memory section and a second memory section, and before an OTPmemory block is programmed, each memory cell of the OTP memory blockstoring a first logic value, the method comprising: selecting a firsttarget memory block; and programming the second memory section of thefirst target memory block such that the second memory section stores apredetermined value to erase the first target memory block.
 7. Themethod of claim 6, wherein the memory device comprises a plurality ofOTP memory blocks arranged in sequence, and the method furthercomprises: writing a to-be-written data to a second target memory blockthat is after the first target memory block, wherein if theto-be-written data corresponds to the predetermined value, program onlythe first memory section of the second target memory block to store afirst data, and if the to-be-written data does not correspond to thepredetermined value, program the second memory section of the secondtarget memory block according to the to-be-written data.
 8. The methodof claim 6, wherein the memory device comprises M OTP memory blocks, andthe step of selecting the first target memory block further comprises:comparing the second memory sections of N OTP memory blocks from the MOTP memory blocks according to a search rule to select the first targetmemory block.
 9. The method of claim 8, wherein the search rule is asequential search or a binary search.
 10. A method for accessing amemory device, the memory device comprising at least oneone-time-programmable (OTP) memory block, each memory block comprising afirst memory section and a second memory section, and before an OTPmemory block is programmed, each memory cell of the OTP memory blockstoring a first logic value, the method comprising: selecting a targetmemory block; and writing a to-be-written data to the target memoryblock, wherein if the to-be-written data corresponds to a predeterminedvalue, program only the first memory section of the target memory blockto store a first data, and if the to-be-written data does not correspondto the predetermined value, program the second memory section of thetarget memory block according to the to-be-written data.
 11. The methodof claim 10, further comprising: reading the target memory block; and ifthe first memory section of the target memory block stores the firstdata, the predetermined value is outputted as the value stored in thetarget memory block, and if the first memory section of the targetmemory block stores a second data, the value stored in the second memorysection of the target memory block is outputted as the value stored inthe target memory block.
 12. The method of claim 10, wherein the memorydevice comprises M OTP memory blocks, and the step of selecting thetarget memory block further comprises: comparing the second memorysections of N OTP memory blocks from the M OTP memory blocks accordingto a search rule to select the target memory block.
 13. The method ofclaim 12, wherein the search rule is a sequential search or a binarysearch.